Gallium nitride material devices including an electrode-defining layer and methods of forming the same

ABSTRACT

Gallium nitride material devices and methods of forming the same are provided. The devices include an electrode-defining layer. The electrode-defining layer typically has a via formed therein in which an electrode is formed (at least in part). Thus, the via defines (at least in part) dimensions of the electrode. In some cases, the electrode-defining layer is a passivating layer that is formed on a gallium nitride material region.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.10/740,376, filed Dec. 17, 2003, which is incorporated herein byreference.

FIELD OF INVENTION

The invention relates generally to gallium nitride materials and, moreparticularly, to gallium nitride material devices including anelectrode-defining layer and methods of forming the same.

BACKGROUND OF INVENTION

Gallium nitride materials include gallium nitride (GaN) and its alloyssuch as aluminum gallium nitride (AlGaN), indium gallium nitride(InGaN), and aluminum indium gallium nitride (AlInGaN). These materialsare semiconductor compounds that have a relatively wide, direct bandgapwhich permits highly energetic electronic transitions to occur. Galliumnitride materials have a number of attractive properties including highelectron mobility, the ability to efficiently emit blue light, theability to transmit signals at high frequency, and others. Accordingly,gallium nitride materials are being widely investigated in manymicroelectronic applications such as transistors, field emitters, andoptoelectronic devices.

SUMMARY OF INVENTION

The invention provides gallium nitride material devices including anelectrode-defining layer and methods of forming the same.

In one embodiment, a semiconductor structure is provided. The structurecomprises a gallium nitride material region and an electrode-defininglayer formed over the gallium nitride material region. Theelectrode-defining layer includes a via formed therein. Across-sectional area at a top of the via is greater than across-sectional area at a bottom of the via. The structure furthercomprises an electrode formed on the gallium nitride material region andin the via, wherein the electrode length is defined at the bottom of thevia.

In another embodiment, a transistor is provided. The transistorcomprises a gallium nitride material region and an electrode-defininglayer formed on the gallium nitride material region. Theelectrode-defining layer includes a via formed therein. Across-sectional area of the via is greater at a top of the via than at abottom of the via. A sidewall of the via extends upward from the bottomof the via at an angle between about 5 degrees and about 85 degrees anddownward from the top of the via at an angle between about 90 degreesand about 160 degrees. The transistor further comprises a sourceelectrode formed on the gallium nitride material region, a drainelectrode formed on the gallium nitride material region; and a gateelectrode formed on the gallium nitride material region and in the via.A length of the gate electrode is defined at the bottom of the via andthe ratio of the gate electrode length to a cross-sectional dimension atthe top of the via is between about 0.50 and 0.95.

In another embodiment, a Schottky diode is provided. The Schottky diodecomprises a gallium nitride material region and an electrode-defininglayer formed over the gallium nitride material region. Theelectrode-defining layer includes a via formed therein. Across-sectional area at a top of the via is greater than across-sectional area at a bottom of the via. A sidewall of the viaextends upward from the bottom of the via at an angle between about 5degrees and about 85 degrees and downward from the top of the via at anangle between about 90 degrees and about 160 degrees. The Schottky diodefurther comprises a Schottky electrode formed on the gallium nitridematerial region and in the via, wherein the electrode length is definedat the bottom of the via. The Schottky diode further comprises an ohmicelectrode formed on the gallium nitride material region.

In another embodiment, a method of forming a semiconductor structure isprovided. The method comprises forming an electrode-defining layer on agallium nitride material region and forming a via in theelectrode-defining layer such that a cross-sectional dimension at a topof the via is greater than a cross-sectional dimension at a bottom ofthe via. The method further comprises forming an electrode on thegallium nitride material region and in the via, wherein a length of theelectrode is defined by the bottom of the via.

In another embodiment, a method of forming a transistor is provided. Themethod comprises forming an electrode-defining layer on a galliumnitride material region and forming a via in the electrode-defininglayer. A cross-sectional dimension at a top of the via is greater than across-sectional dimension at a bottom of the via and a sidewall of thevia extends upward from the bottom of the via at an angle between about5 degrees and about 85 degrees and downward from the top of the via atan angle between about 90 degrees and about 160 degrees. The methodfurther comprises forming a source electrode on the gallium nitridematerial region, forming a drain electrode on the gallium nitridematerial region, and forming a gate electrode on the gallium nitridematerial region and in the via. A length of the gate electrode isdefined at the bottom of the via and the ratio of the gate electrodelength to a cross-sectional dimension at the top of the via is betweenabout 0.50 and 0.95.

In another embodiment, a method of forming a Schottky diode is provided.The method comprises forming an electrode-defining layer on a galliumnitride material region and forming a via in the electrode-defininglayer. A cross-sectional dimension at a top of the via is greater than across-sectional dimension at a bottom of the via. A sidewall of the viaextends upward from the bottom of the via at an angle between about 5degrees and about 85 degrees and downward from the top of the via at anangle between about 90 degrees and about 160 degrees. The method furthercomprises forming an ohmic electrode on the gallium nitride materialregion and forming a Schottky electrode on the gallium nitride materialregion and in the via, wherein the electrode length is defined at thebottom of the via.

Other aspects, embodiments and features of the invention will becomeapparent from the following detailed description of the invention whenconsidered in conjunction with the accompanying drawings. Theaccompanying figures are schematic and are not intended to be drawn toscale. In the figures, each identical, or substantially similarcomponent that is illustrated in various figures is represented by asingle numeral or notation. For purposes of clarity, not every componentis labeled in every figure. Nor is every component of each embodiment ofthe invention shown where illustration is not necessary to allow thoseof ordinary skill in the art to understand the invention. All patentapplications and patents incorporated herein by reference areincorporated by reference in their entirety. In case of conflict, thepresent specification, including definitions, will control.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1A is a cross-section of a gallium nitride material deviceincluding an electrode-defining layer according to an embodiment of theinvention.

FIG. 1B is a top view of the gallium nitride material device of FIG. 1A.

FIG. 2 shows the profile of an electrode-defining layer according to anembodiment of the invention.

FIG. 3 is a cross-section of a gallium nitride material device includingan electrode-defining layer that includes a via that extends only aportion through the thickness of the electrode-defining layer accordingto an embodiment of the invention.

FIG. 4 is a cross-section of a gallium nitride material device includinga passivating layer formed between the electrode-defining layer andgallium nitride material region according to an embodiment of theinvention.

FIGS. 5A and 5B respectively are a top view and a cross-section of aSchottky diode according to an embodiment of the invention.

FIG. 6 is a cross-section of a semiconductor structure after ametallization step according to a method of the invention.

FIG. 7 is a cross-section of a semiconductor structure after depositionof an electrode-defining layer according to a method of the invention.

FIG. 8 is a cross-section of a semiconductor structure during animplantation step according to a method of the invention.

FIG. 9 is a cross-section of a semiconductor structure after aphotoresist patterning step according to a method of the invention.

FIG. 10 is a cross-section of a semiconductor structure after aelectrode-defining layer etching step according to a method of theinvention.

FIG. 11 is a cross-section of a semiconductor structure after ametallization step according to a method of the invention.

FIG. 12 is a cross-section of a semiconductor structure after anencapsulation step according to a method of the invention.

FIG. 13A shows the cross-section of a T-shaped gate electrode of a FETdevice of the present invention as described in Example 1.

FIG. 13B shows the cross-section a trapezoidal-shaped gate electrode ofa conventional FET device as described in Example 1.

FIGS. 13C and 13D are two-dimensional electric field simulations at thedrain edge of the gate electrodes of FIGS. 10A and 10B, respectively, asdescribed in Example 1.

FIG. 14 shows drain leakage current as a function of drain-sourcevoltage for the devices described in Example 2.

FIG. 15 is a cross-section of a gallium nitride material device thatincludes a gate electrode height that is less than the thickness of thepassivating layer according to an embodiment of the invention.

DETAILED DESCRIPTION

The invention provides gallium nitride material devices and methods offorming the same. The devices include an electrode-defining layer. Theelectrode-defining layer typically has a via formed therein in which anelectrode is formed (at least in part). Thus, the via defines (at leastin part) dimensions of the electrode. In some cases, theelectrode-defining layer is a passivating layer that is formed on agallium nitride material region.

FIGS. 1A and 1B illustrate a semiconductor device 10 that includes agallium nitride material region 12 according to one embodiment of theinvention. In the illustrative embodiment, device 10 is a field effecttransistor (FET) that includes a source electrode 14, a drain electrode16 and a gate electrode 18 formed on the gallium nitride materialregion. The gallium nitride material region is formed on a substrate 20and, as shown, a transition layer 22 may be formed between the substrateand the gallium nitride material region. The device includes anelectrode-defining layer 24 which, as shown, is a passivating layer thatprotects and passivates the surface of the gallium nitride materialregion. A via 26 is formed within layer 24 in which the gate electrodeis, in part, formed. As described further below, the shape anddimensions of the via and, thus the gate electrode, can be controlled toimprove properties of the device.

Though in the illustrative embodiment of FIGS. 1A and 1B device 10 is aFET, the invention encompasses other types of devices as describedfurther below. It should be understood that in non-FET embodiments ofthe invention, the electrode-defining layer may define other types ofelectrode than gate electrodes, such as Schottky contacts. Also, thoughthe electrode-defining layer in FIGS. 1A and 1B functions as apassivating layer, in other embodiments the electrode-defining layer maynot function as a passivating layer (e.g., see FIG. 4).

When a layer is referred to as being “on” or “over” another layer orsubstrate, it can be directly on the layer or substrate, or anintervening layer also may be present. A layer that is “directly on”another layer or substrate means that no intervening layer is present.It should also be understood that when a layer is referred to as being“on” or “over” another layer or substrate, it may cover the entire layeror substrate, or a portion of the layer or substrate.

As used herein, the term “passivating layer” refers to any layer thatwhen grown on an underlying layer (e.g. gallium nitride material region12) reduces the number and/or prevents formation of surface/interfacestates in the bandgap of the underlying layer, or reduces the numberand/or prevents formation of free carrier (e.g., electron or hole)trapping states at the surface/interface of the underlying layer. Thetrapping states, for example, may be associated with surface statescreated by unterminated chemical bonds, threading dislocations at thesurface or ions adsorbed to the surface from the environment. In a FETdevice, the trapping states may capture free carriers or may createundesired depletion regions during DC or RF operation. These effects maycause a decrease in the amount of current that otherwise would flow in achannel of the FET during operation, thus, impairing the performance ofthe device. The passivating layer may substantially reduce these effectsthereby improving electrical performance of the device such as increasedoutput power or efficiency. The passivating layer may also increase thebreakdown voltage of the device.

It should be understood that a passivating layer may also protect theunderlying layer (e.g. gallium nitride material region 12) duringsubsequent processing steps including photolithography, etching, metal(e.g., gate, interconnect) deposition, implantation, wet chemical, andresist strip (e.g., in a plasma) steps. Thus, a passivating layer maylimit or eliminate reactions and/or interactions of other processingspecies (e.g., liquids, ions, plasmas, gaseous species) with the surfaceof the gallium nitride material. These reactions and/or interactions canbe detrimental to the electrical properties of the device by changingsurface morphology, the number of surface states, the amount of surfacecharge, the polarity of surface charge, or any combination of these.

Suitable compositions for electrode-defining layer 24 include, but arenot limited to, nitride-based compounds (e.g., silicon nitridecompounds), oxide-based compounds (e.g., silicon oxide compounds),polyimides, other dielectric materials, or combinations of thesecompositions (e.g., silicon oxide and silicon nitride). In some cases,it may be preferable for the electrode-defining layer to be a siliconnitride compound (e.g., Si₃N₄) or non-stoichiometric silicon nitridecompounds. It should be understood that these compositions are suitablewhen the electrode-defining layer functions as a passivating layer (asshown in FIGS. 1A and 1B) and also when the electrode-defining layerdoes not function as a passivating layer.

The thickness of electrode-defining layer 24 depends on the design ofthe device. In some cases, the electrode-defining layer may have athickness of between about 50 Angstroms and 1.0 micron. In some cases,the thickness may be between about 700 Angstroms and about 1200Angstroms.

As shown, electrode-defining layer 24 covers the entire surface ofgallium nitride material region 12 with the exception of the electroderegions (source 14, drain 16 and gate 18).

The following designations are used in FIGS. 1-2 to represent the noteddimensions: gate length (i.e., cross-sectional dimension of gate atbottom of the via) (a), cross-sectional dimension at top of the via (b),electrode-defining layer thickness (c), source electrode side overhangdistance (d), drain electrode side overhang distance (e), gate-sourcespacing (f), gate-drain spacing (g), and gate electrode height (h).

It should be understood that the cross-sectional dimensions referred toabove are measured in a plane P (FIG. 1B) that is perpendicular to thesource and drain electrodes and defines the minimum distancetherebetween.

FIG. 2 illustrates the profile of the via and corresponding gateelectrode. An angle Z is the angle that a sidewall 28 of theelectrode-defining layer extends upward from a bottom surface 30 of theelectrode-defining layer and an angle Y is the angle that the sidewallextends downward from a top surface 32 of the electrode-defining layer.It should be understood that angles Y and Z are respectively measured atbottom and top surfaces 30, 32 and that sidewall 28 may deviate fromthese angles at distances away from the bottom and top surfaces.

Though the above-noted dimensions and angles are shown relative to thegate electrode in the FET embodiments of FIGS. 1 and 2, some of thesedimensions and angles may also be applied to other types of electrodesin non-FET embodiments as described further below.

Advantageously, methods of forming devices of the invention, describedfurther below, allow definition of gate electrode dimensions (e.g., a)entirely within the electrode-defining layer. This is to bedistinguished from processes that form gate electrodes prior toelectrode-defining layer deposition, or processes that define a portionof the gate electrode within a electrode-defining layer but not gatelength (a). Such processes that form a portion of the gate electrodewithin a electrode-defining layer but, for example, may include regions(e.g., regions proximate bottom surface 30 that undercut theelectrode-defining layer) within the via that are not completely filledby gate electrode material. In these processes, the gate length,therefore, may not be entirely defined by the electrode-defining layer.In contrast, in some preferred methods of the present invention, theentire via (or, at least, regions of the via at bottom surface 30) isfilled with the gate electrode material so that the dimensions of thevia precisely correspond to gate dimensions and, in particular, the gatelength. Thus, using the methods of the invention, critical electrodedimensions (e.g., gate length) can be precisely controlled to optimizedevice performance. One aspect of the invention is the discovery thatcertain gate electrode dimensions (including the gate electrode profile)lead to performance improvements in FET device 10.

It should be understood that in certain methods of the invention regionsof the via at or proximate top surface 32 may not be filled with gateelectrode material if gate electrode height (h) is less than theelectrode-defining layer thickness (c) (See FIG. 15).

In the illustrative embodiment of FIGS. 1A and 1B, gate length (a) issmaller than cross-sectional dimension at the top of the via (b). Via 26(and, thus, gate electrode 18) also has a larger cross-sectional area atthe top of the via than a cross-sectional area at the bottom of the via.As shown, the cross-sectional area of the via (and, thus gate electrode)decreases from the top of the via to the bottom of the via. It may bepreferable for sidewalls 28 to have a straight (uncurved) slope. In somecases, it may be preferable for sidewalls 28 to have a curved slope. Insome cases when the sidewalls have a curved slope, the sidewalls mayhave a concave-up shape in relation to gallium nitride material region12 as shown. As described further below, the electrode-defining layeretching step may be controlled to provide the desired gate profile. Itshould be understood that the cross-sectional areas of the via (andelectrodes) are measured in planes that are parallel to the planedefined by the electrode-defining layer as shown.

It has been discovered that the ratio of (a)/(b) can be an importantdesign parameter for device 10 that affects the breakdown voltage. Insome embodiments of the invention, the ratio of (a)/(b) is controlled tobe between about 0.50 and about 0.95. In some cases, it may be preferredto control the ratio to be between about 0.75 and about 0.90. Values of(a)/(b) ratios within these ranges can improve the breakdown voltage.The optimal value of the (a)/(b) ratio depends on the specific deviceand also can depend on other design parameters. As described furtherbelow, parameters of the electrode-defining layer etching step may becontrolled to provide the desired (a)/(b) ratio.

The absolute value of gate length (a) depends on the particular devicedesign. For example, (a) may be between about 0.1 micron and about 5.0micron. However, it should be understood that other values for (a) mayalso be suitable.

It has also been discovered that angles Y and Z have preferred rangesfor device operation. It may be preferable for angle Z to be less than90 degrees. For example, it may be preferable for angle Z to be betweenabout 5 degrees and about 85 degrees; in some cases, between about 10degrees and about 60 degrees; and, in some cases, between about 15degrees and about 40 degrees. It may be preferable for angle Y to begreater than 90 degrees. Angle Y typically is between about 90 degreesand about 160 degrees. It may be preferred for angle Y to be betweenabout 90 degrees and about 135 degrees; and, in some cases, betweenabout 90 degrees and about 110 degrees.

It has been determined that angles Y and Z affect the location andstrength of electrical fields generated by the device. By controllingthe values of Y and Z within the above ranges, the peak electric fieldestablished near the drain edge of the gate electrode during deviceoperation can be reduced. This improvement may lead to increasedoperating voltage and/or reduced gate leakage current. If the values ofY and Z are outside the above ranges, the peak electric fieldestablished near the drain edge of the gate electrode may be too highwhich can lead to excessive gate leakage current and/or pre-maturedevice failure.

The above-noted ranges of angles Y and Z are also important in promotingcomplete filling of the via with gate electrode material. The optimalvalue(s) of angles Y and Z depend on the specific device and also candepend on other design parameters. The electrode-defining layer etchingstep may be controlled to provide the desired values of angles Y and Z,as described further below.

As described further below, angles Y and Z may also be important innon-FET devices such as Schottky diodes (e.g., See FIGS. 5A and 5B).

It should be understood that the angles referred to herein are to bemeasured on a microscopic scale (e.g., dimensions of greater than about50 or 100 Angstroms), for example using an SEM (as shown in FIG. 13A).The angles are not intended to be measured on an atomic scale, forexample using a TEM, which indicates the presence surface effects (e.g.,monolayers of atoms) that may distort values of the angles.

It is also preferred for the gate electrode to have a T-shape designwhich includes portions that overhang underlying electrode-defininglayer 24. It has been determined that drain electrode side overhangdistance (e) is particularly important in effecting the breakdownvoltage of the device. The portion of the gate electrode that overhangsthe electrode-defining layer in the direction of the drain electrode canfunction as a field plate which increases the breakdown voltage of thedevice, amongst other beneficial effects. It has been observed that thebreakdown voltage may be increased, for example, when (e) is betweenabout 2 percent and about 60 percent of the gate drain spacing (g). Insome cases, it may be preferred for (e) to be between about 10 percentand about 50 percent of (g) to further optimize the breakdown voltage ofthe device. The optimal value(s) of (e) depend on the specific deviceand also can depend on other design parameters.

It has also been observed that it is advantageous to control the sourceelectrode side overhang distance (d) to be less than drain electrodeside overhang distance (e). In some cases, it is preferable to have (d)be less than 50 percent of (e), or even less than 20% of (e). In somecases, it is advantageous to minimize (d) while ensuring that the entirevia is filled. Reducing the value of (d) limits, or prevents, unwantedgate-source capacitance.

The values of (d) and (e) are controlled, in part, by the metaldeposition and patterning steps described further below.

The absolute values of the source electrode side overhang distance (d),drain electrode side overhang distance (e), gate-source spacing (f) andgate-drain spacing (g) depend on the device design. Typical values of(f) and (g) are between about 0.1 micron and about 10 micron, thoughother values are possible.

In some embodiments, the value of the gate electrode height (h) isgreater than the value of the electrode-defining layer thickness (c)(See FIG. 1A). In other embodiments, the value of the gate electrodeheight (h) is less than the value of the electrode-defining layerthickness (c) (See FIG. 15). Though not as critical as other gatedimensions, preferred values of (h) depend on the specific device andalso can depend on other design parameters. For example, (h) may bebetween about 100 Angstroms and 2.0 micron. The value of (h) may becontrolled by processing conditions used to deposit the gate electrodematerial as described further below.

Gate electrode 18 may be formed of any suitable conductive material suchas metals (e.g., Au, Ni), metal compounds (e.g., WSi, WSiN), alloys,semiconductors, polysilicon, nitrides, or combinations of thesematerials. For example, the gate electrode may be formed of gold, nickelor both. Advantageously, forming the gate electrode in via 26 enablesformation of gate electrodes that include a single conductive materialcomponent (e.g., nickel) in direct contact with the gallium nitridematerial region across the entire gate length, even in cases when thegate electrode also includes a second conductive material component. Forexample, when the gate electrode is formed of nickel and gold, thenickel layer may be in direct contact with the gallium nitride materialregion across the entire gate length and the gold layer may be formedover the nickel layer (e.g., see FIG. 13A). In contrast, prior arttechniques for forming gate electrodes that include multiple metalcompositions may have a first component (e.g., nickel) that is in directcontact with interior portions of the gate length and a second component(e.g., gold) in direct contact with edge portions of the gate length(e.g., see FIG. 13B). Providing a single component in direct contactwith the gallium nitride material region across the entire gate lengthcan improve electrical properties, such as reducing gate leakagecurrent, by eliminating losses that may occur when a second component isin direct contact with portions of the gate length. Furthermore, whenmultiple components are in direct contact with the gallium nitridematerial region, the Schottky barrier height of the gate electrode maynot be controlled by material composition.

It should also be understood that the source and drain electrodes 14 and16 may also be formed of any suitable conducting material including thesame materials described above in connection with the gate electrode, aswell as Ti, Al, Pt or Si.

In certain preferred embodiments, substrate 20 is a silicon substrate.As used herein, a silicon substrate refers to any substrate thatincludes a silicon surface. Examples of suitable silicon substratesinclude substrates that are composed entirely of silicon (e.g., bulksilicon wafers), silicon-on-insulator (SOI) substrates,silicon-on-sapphire substrate (SOS), and SIMOX substrates, amongstothers. Suitable silicon substrates also include substrates that have asilicon wafer bonded to another material such as diamond, AlN, or otherpolycrystalline materials. Silicon substrates having differentcrystallographic orientations may be used. In some cases, silicon (111)substrates are preferred. In other cases, silicon (100) substrates arepreferred.

It should be understood that other types of substrates may also be usedincluding sapphire, silicon carbide, gallium nitride and aluminumnitride substrates.

Substrate 20 may have any suitable dimensions and its particulardimensions are dictated by the application. Suitable diameters include,but are not limited to, 2 inches (50 mm), 4 inches (100 mm), 6 inches(150 mm), and 8 inches (200 mm). In some embodiments, substrate 20 isrelatively thick, for example, greater than 250 microns. Thickersubstrates are generally able to resist bending which can occur, in somecases, in thinner substrates. In other embodiments, thinner substrates(e.g., less than 250 microns) are used.

Transition layer 22 may be formed on substrate 20 prior to thedeposition of gallium nitride material region 12. The transition layermay accomplish one or more of the following: reducing crack formation inthe gallium nitride material region 12 by lowering thermal stressesarising from differences between the thermal expansion rates of galliumnitride materials and the substrate; reducing defect formation ingallium nitride material region by lowering lattice stresses arisingfrom differences between the lattice constants of gallium nitridematerials and the substrate; and, increasing conduction between thesubstrate and gallium nitride material region by reducing differencesbetween the band gaps of substrate and gallium nitride materials. Thepresence of the transition layer may be particularly preferred whenutilizing silicon substrates because of the large differences in thermalexpansion rates and lattice constant between gallium nitride materialsand silicon. It should be understood that the transition layer also maybe formed between substrate 20 and gallium nitride material region for avariety of other reasons. In some cases, for example when a siliconsubstrate is not used, the device may not include a transition layer.

The composition of transition layer 22 depends, at least in part, on thetype of substrate and the composition of gallium nitride material region12. In some embodiments which utilize a silicon substrate, thetransition layer may preferably comprise a compositionally-gradedtransition layer having a composition that is varied across at least aportion of the layer. Suitable compositionally-graded transition layers,for example, have been described in commonly-owned U.S. Pat. No.6,649,287, entitled “Gallium Nitride Materials and Methods,” filed onDec. 14, 2000, which is incorporated herein by reference.Compositionally-graded transition layers are particularly effective inreducing crack formation in the gallium nitride material region bylowering thermal stresses that result from differences in thermalexpansion rates between the gallium nitride material and the substrate(e.g., silicon). In some embodiments, when the compositionally-graded,transition layer is formed of an alloy of gallium nitride such asAl_(x)In_(y)Ga_((1-x-y))N, Al_(x)Ga_((1-x))N, or In_(y)Ga_((1-y))N,wherein 0≦x≦1, 0≦y≦1. In these embodiments, the concentration of atleast one of the elements (e.g., Ga, Al, In) of the alloy is typicallyvaried across at least a portion of the cross-sectional thickness of thelayer. In some cases, the transition layer has a monocrystallinestructure.

In other embodiments, transition layer 22 has a constant (i.e.,non-varying) composition across its thickness. Such transition layersmay also be referred to as buffer layers.

In some embodiments, device 10 may also optionally include other layersthat are not depicted in the figures. For example, device 10 may includeone or more intermediate layers. An intermediate layer may be formed,for example, between the substrate and the transition layer (e.g., acompositionally-graded transition layer) and/or between the transitionlayer and the gallium nitride material region. Suitable intermediatelayers, for example, have been described and illustrated in U.S. Pat.No. 6,649,287, which was incorporated by reference above. In someembodiments, the intermediate layer may have a constant composition of agallium nitride alloy (such as Al_(x)In_(y)Ga_((1-x-y))N,Al_(x)Ga_((1-x))N, or In_(y)Ga_((1-y))N), aluminum nitride, or analuminum nitride alloy. In some cases, the intermediate layer(s) have amonocrystalline structure.

Gallium nitride material region 12 comprises at least one galliumnitride material layer. As used herein, the phrase “gallium nitridematerial” refers to gallium nitride (GaN) and any of its alloys, such asaluminum gallium nitride (Al_(x)Ga_((1-x))N), indium gallium nitride(In_(y)Ga_((1-y))N), aluminum indium gallium nitride(Al_(x)In_(y)Ga_((1-x-y))N), gallium arsenide phosporide nitride(GaAs_(a)P_(b)N_((1-a-b))), aluminum indium gallium arsenide phosporidenitride (Al_(x)In_(y)Ga_((1-x-y))As_(a)P_(b)N_((1-a-b))), amongstothers. Typically, when present, arsenic and/or phosphorous are at lowconcentrations (i.e., less than 5 weight percent). In certain preferredembodiments, the gallium nitride material has a high concentration ofgallium and includes little or no amounts of aluminum and/or indium. Inhigh gallium concentration embodiments, the sum of (x+y) may be lessthan 0.4, less than 0.2, less than 0.1, or even less. In some cases, itis preferable for the gallium nitride material layer to have acomposition of GaN (i.e., x+y=0). Gallium nitride materials may be dopedn-type or p-type, or may be intrinsic. Suitable gallium nitridematerials have been described in U.S. Pat. No. 6,649,287, incorporatedby reference above.

In some cases, gallium nitride material region 12 includes only onegallium nitride material layer. In other cases, gallium nitride materialregion 12 includes more than one gallium nitride material layer. Thedifferent layers can form different regions of the semiconductor device.Gallium nitride material region 12 also may include one or more layersthat do not have a gallium nitride material composition such as otherIII-V compounds or alloys, oxide layers, and metallic layers.

Gallium nitride material region 12 is of high enough quality so as topermit the formation of devices therein. Preferably, gallium nitridematerial region 12 has a low crack level and a low defect level. Asdescribed above, transition layer 22 (particularly whencompositionally-graded) may reduce crack and/or defect formation. Insome embodiments, the gallium nitride material region has about 10⁹defects/cm². Gallium nitride materials having low crack levels have beendescribed in U.S. Pat. No. 6,649,287 incorporated by reference above. Insome cases, the gallium nitride material region a crack level of lessthan 0.005 μm/μm². In some cases, the gallium nitride material regionhas a very low crack level of less than 0.001 μm/μm². In certain cases,it may be preferable for gallium nitride material region to besubstantially crack-free as defined by a crack level of less than 0.0001μm/μm².

In certain cases, gallium nitride material region 12 includes a layer orlayers which have a monocrystalline structure. In some cases, thegallium nitride material region includes one or more layers having aWurtzite (hexagonal) structure.

The thickness of gallium nitride material region 12 and the number ofdifferent layers are dictated, at least in part, by the requirements ofthe specific device. At a minimum, the thickness of gallium nitridematerial region 12 is sufficient to permit formation of the desireddevice. Gallium nitride material region 12 generally has a thickness ofgreater than 0.1 micron, though not always. In other cases, galliumnitride material region 12 has a thickness of greater than 0.5 micron,greater than 0.75 micron, greater than 1.0 microns, greater than 2.0microns, or even greater than 5.0 microns.

FIG. 3 illustrates a semiconductor device 40 according to anotherembodiment of the invention. In the embodiment of FIG. 3, via 26 extendsonly a portion of the way through the thickness of electrode-defininglayer 24. Thus, a portion of the electrode-defining layer remainsbetween gate electrode 18 and gallium nitride material region 12. Insome embodiments, it is preferred that the electrode-defining layer isformed of an insulating material such as silicon oxide, silicon nitride,polyimides, other dielectric materials, or combinations of thesecompositions (e.g., silicon oxide and silicon nitride). In embodimentsin which the electrode-defining layer is formed of an insulatingmaterial, device 40 forms a MISFET (metal-insulator-semiconductor).

FIG. 4 illustrates a semiconductor device 42 according to anotherembodiment of the invention. Device 42 includes a layer 43 formedbetween electrode-defining layer 24 and gallium nitride material region12. Layer 43 has a different composition than electrode-defining layer24. In some cases, it is preferred that layer 43 is a passivating layer.Suitable passivating layer compositions have been described above. Itshould be understood that, in some cases, more than one layer may beformed between the electrode-defining layer and the gallium nitridematerial region.

FIGS. 5A and 5B illustrate a semiconductor device 44 according toanother embodiment of the invention. In this embodiment, device 44 is aSchottky diode that includes a Schottky electrode (i.e., Schottkycontact) 46 defined (in part) within via 26. Device 44 also includes anohmic electrode 48 that is formed around the diameter of the structure.

The above-noted ranges of angles Y and Z in connection with the FETembodiment are also important in Schottky diode embodiments (and otherdevices). In particular, values of Y and Z within the above-noted rangespromote complete filling of the via with electrode material, amongstother advantages. The optimal value(s) of angles Y and Z depend on thespecific device and also can depend on other design parameters. Theelectrode-defining layer etching step may be controlled to provide thedesired values of angles Y and Z, as described further below.

It is also preferred for Schottky electrode 46 to have a T-shape designwhich includes portions that overhang underlying electrode-defininglayer 24, as described in connection with the FET embodiment of FIGS. 1Aand 1B. It has been determined that overhang distance (i) isparticularly important in affecting the breakdown voltage of the device.The portion of the Schottky electrode that overhangs theelectrode-defining layer in the direction of the ohmic electrode canfunction as a field plate which increases the breakdown voltage of thedevice, amongst other beneficial effects. It has been observed that thebreakdown voltage may be increased, for example, when (i) is betweenabout 2 percent and about 60 percent of a distance (j) between theSchottky electrode and the ohmic electrode. In some cases, it may bepreferred for (i) to be between about 10 percent and about 50 percent of(j) to further optimize the breakdown voltage of the device. The optimalvalue(s) of (j) depend on the specific device and also can depend onother design parameters.

It should be understood that Schottky diodes of the invention may alsohave a non-circular layout.

It should also be understood that although the present invention hasbeen described above in connection with a transistor and Schottky diode,the invention may encompass other devices. For example, other electronicor electro-optical devices may use a electrode-defining layer (which, insome cases, may also function as a passivating layer). Suitable devicesinclude Schottky rectifiers, Gunn-effect diodes, varactor diodes,voltage-controlled oscillators, light emitting diodes, lasers orphotodetectors.

FIGS. 6-11 show cross-sections of the resulting semiconductor structureafter different processing steps according to one illustrative method ofthe present invention. Though FIGS. 6-11 show the production of a FETaccording to one method of the invention, it should also be understoodthat other devices of the invention may be produced using similar methodsteps.

FIG. 6 shows a cross-section of the structure after deposition ofgallium nitride material region 12 and transition layer 22 on substrate20 and deposition of source and drain electrodes 14 and 16.

Transition layer 22 and gallium nitride material region 12 may bedeposited on substrate 20, for example, using metalorganic chemicalvapor deposition (MOCVD), molecular beam epitaxy (MBE), and hydridevapor phase epitaxy (HVPE), amongst other techniques. In some cases, anMOCVD process may be preferred. A suitable MOCVD process to form acompositionally-graded transition layer and gallium nitride materialregion over a silicon substrate has been described in U.S. Pat. No.6,649,287 incorporated by reference above. When gallium nitride materialregion 12 has different layers, in some cases it is preferable to use asingle deposition step (e.g., an MOCVD step) to form the entire region12. When using the single deposition step, the processing parameters aresuitably changed at the appropriate time to form the different layers.In certain preferred cases, a single growth step may be used to form thetransition layer and gallium nitride material region.

In other embodiments of the invention (not shown), it is possible togrow gallium nitride material region 12 using a lateral epitaxialovergrowth (LEO) technique that involves growing an underlying galliumnitride layer through mask openings and then laterally over the mask toform the gallium nitride material region, for example, as described inU.S. Pat. No. 6,051,849, which is incorporated herein by reference. Themask regions are not shown in the figures.

In other embodiments of the invention (not shown), it is possible togrow region 12 using a pendeoepitaxial technique that involves growingsidewalls of gallium nitride material posts into trenches until growthfrom adjacent sidewalls coalesces to form a gallium nitride materialregion, for example, as described in U.S. Pat. No. 6,177,688, which isincorporated herein by reference. In these lateral growth techniques,gallium nitride material regions with very low defect densities areachievable. For example, at least a portion of the gallium nitridematerial region may have a defect density of less than about 10⁵defects/cm².

Source and drain electrodes 14, 16 may be deposited on the galliumnitride material region using known techniques such as an evaporationtechnique. In cases when the electrodes include two metals, then themetals are typically deposited in successive steps. The deposited metallayer may be patterned using conventional methods to form theelectrodes.

The structure shown in FIG. 6 may be subjected to a rapid thermalannealing (RTA) step in which, for example, the structure is heated totemperatures of between about 500 degrees C. and 1000 degrees C. In somecases, the temperature may be between about 800 degrees C. and 900degrees C. The annealing step is performed to promote alloying of thedifferent materials in the source and drain electrodes and to promoteformation of intimate contact between these electrodes and theunderlying gallium nitride material region.

FIG. 7 shows a cross-section of the semiconductor structure after thedeposition of electrode-defining layer 24. As shown, electrode-defininglayer 24 covers gallium nitride material region 12 conformally. Theelectrode-defining layer may be deposited using any suitable technique.The technique used, in part, depends on the composition of theelectrode-defining layer. Suitable techniques include, but are notlimited to CVD, PECVD, LP-CVD, ECR-CVD, ICP-CVD, evaporation andsputtering. When the electrode-defining layer is formed of a siliconnitride material, it may be preferable to use PECVD to deposit thelayer.

As noted above, depositing the electrode-defining layer prior toformation of the gate electrode advantageously enables theelectrode-defining layer to passivate and protect the gallium nitridematerial region during subsequent processing steps including the step offorming the gate electrode. It should be understood that in othermethods of the invention that the electrode-defining layer may bedeposited prior to the deposition of the source and drain electrodes. Inthese embodiments, respective vias are opened in the electrode-defininglayer, for example using etching techniques, to enable contact betweenthe source and drain electrodes and the underlying gallium nitridematerial region.

FIG. 8 illustrates a cross-section of the structure during an ionimplantation step. A photoresist layer 34 a is patterned to exposeregions on respective sides of the drain and source electrodes. In theillustrative embodiment, nitrogen ions are implanted in the exposedregions to form amorphized gallium nitride material regions 35underlying the regions. The amorphized regions electrically isolate thedevices from adjacent devices formed on the same wafer.

It should be understood that other types of ions may also be used in theimplantation step or other techniques for isolating adjacent devices maybe utilized. In some cases, adjacent devices may be isolated using anetching step that removes the electrode-defining layer, as well as aportion of the gallium nitride material region. The optimal value of theetch depth depends on the specific device and also can depend on otherdesign parameters. In other cases, it may not be necessary to isolateadjacent devices and, thus, the implant step is not required.

FIG. 9 illustrates a cross-section of the structure after thephotoresist layer 34 a has been stripped and a second photoresist layer34 b has been patterned.

FIG. 10 illustrates a cross-section of the semiconductor structure afterphotoresist layer 34 b has been stripped and after electrode-defininglayer 24 has been etched. This etching step forms via 26. A plasmaetching technique is preferably used to form the via with controlleddimensions. It has been discovered that certain conventional wetchemical etching techniques do not sufficiently control the critical viadimensions. In some methods, a high density plasma technique (e.g., ICPor ECR) is used to generate the plasma. In other methods, RIE or CAIBEtechniques may be used. Suitable gases that may be ionized to form theplasma include fluorinated hydrocarbons, fluorinated sulfur-based gases,oxygen and argon. Prior to initiation of the etch, an oxygen-based orargon-based plasma treatment may be used to remove any residualhydrocarbon species on the surface of the electrode-defining layer.

Etching conditions may be controlled to form via 26 with the desireddimensions and profile, as described above. One important processingparameter is the pressure conditions in the plasma which largelydetermines the mean free path of the plasma species and, consequently,controls the directionality of the etching. The directionality, oranisotropy, of the etching controls the profile of the via, angle Y, andangle Z, amongst other via dimensions (e.g., a, b). It has beendiscovered that suitable pressure conditions for producing a via havingangles Y and Z may be between about 1-100 mtorr.

RF power is another important process parameter for dry etchingprocesses. The RF power affects the ion energy of species that impingeon the surface of the structure being processed. The ion energy affectsanisotropy of the etching and, therefore, controls the profile of thevia, angles Y and Z, amongst other via dimensions (e.g., a, b). It hasbeen discovered that, in some cases, it may be preferable to maintain RFpower at less than about 50 Watts. In some cases, it may be preferableto maintain RF power at less than about 10 Watts. Using RF power withinthe above ranges may limit, or prevent, plasma-induced damage to thegallium nitride material region which may otherwise be caused whenforming the via.

ICP power is another important processing parameter for etchingprocesses that utilize ICP plasmas. ICP power is measured as the powerapplied to inductive coils outside the walls of a plasma chamber. Thispower creates a magnetic field that confines and creates a dense plasma.The ICP power, therefore, controls the plasma density (relativelyindependent of the ion energy) which in turn can be used to control theetch rate of electrode-defining layer, amongst other parameters. In thisway, the etch rate can be substantially decoupled from the profile ofthe via which allows via dimensions to be tailored. It has beendiscovered that, in some cases, it is preferable to maintain ICP powerbetween about 5 W and about 300 W. In some cases, it may be preferableto maintain ICP power between about 10 W and about 100 W. ICP powervalues above this range may cause detrimental effects to photoresistlayer 34 b, while ICP power values below this range may reduce the etchrate of electrode-defining layer 24 to unacceptable levels.

It should be understood that in certain processes that use an ICP plasmathe RF power may be within the above-described preferred ranges and, insome cases, may be 0.

This etching step can also remove electrode-defining layer 24 from otherexposed regions including those on the source and drain electrodes, aswell as over the implanted regions.

FIG. 11 illustrates a cross-section of the semiconductor structure afterthe gate electrode and interconnect patterning and deposition steps. Thepatterning step is controlled to provide the desired source electrodeside overhang distance (d) and drain electrode side overhang distance(e). Conventional patterning and deposition steps may be used. The gateand interconnects 38 may be patterned and deposited in separate steps orthe same step.

FIG. 12 illustrates a cross-section of the semiconductor structure afterdeposition of an encapsulation layer 52.

It should be understood that the invention encompasses other methodsthan those specifically described herein. Also, variations to the methoddescribed above would be known to those of ordinary skill in the art andare within the scope of the invention.

The following examples are meant to be illustrative and are notlimiting.

EXAMPLE 1

This example shows the effect of gate-electrode shape and composition onelectrical properties by comparing properties of an FET device of thepresent invention to a conventional FET device.

FIG. 13A shows the cross-section of a T-shaped gate electrode of a FETdevice of the present invention. The gate electrode is formed in a viathat decreases in cross-sectional area from the top of the via to thebottom of the via. The electrode is formed of a nickel component and agold component. The nickel component is in direct contact with thegallium nitride material region across the entire gate length includingits edge portions.

FIG. 13B shows the cross-section a trapezoidal-shaped gate electrode ofa conventional FET device. The electrode is formed of a nickel componentand a gold component. The nickel component is in direct contact withinterior portions of the gate length and the gold component is in directcontact with edge portions of the gate length.

FIGS. 13C and 13D are two-dimensional electric field simulations at thedrain edge of the gate electrodes of FIGS. 10A and 10B, respectively.The simulations were performed at V_(DS)=28 V and V_(GS)=0 V. The peakelectric field was 2.4×10⁶ V/cm for the gate electrode of FIG. 10C and6.4×10⁶ V/cm for the gate electrode of FIG. 10D.

The reduced peak electric field for the FET device of the presentinvention compared to the conventional FET device results from reducedfield crowding at the drain edge of the gate electrode. This reductionis attributable to the shape of the gate electrode and, in particular,the shape of the via sidewalls which causes the cross-sectional area ofthe via to decrease from the top of the via to the bottom of the via.The reduction leads to improved electrical performance characteristicsincluding increased operating voltage and/or reduced gate leakagecurrent.

This example establishes that FET devices of the present invention canhave improved electrical properties compared to conventional FETdevices.

EXAMPLE 2

This example shows the affect of varying the drain electrode sideoverhang distance (e) on FET devices of the present invention.

Drain leakage current was measured as a function of drain-source voltagefor two FET devices (Device 1 and Device 2) having the same generaldesign as the device shown in FIGS. 1A and 1B. During the measurements,the gate voltage was maintained constant at a value of −8 Volts.

Devices 1 and 2 included the following dimensions:

-   -   a=0.7 micron    -   b=0.9 micron    -   a/b=0.78    -   d=0.1 micron    -   f=1.0 micron    -   g=3.0 micron    -   h=5.2 micron    -   y=100°    -   z=20°

Device 1 included a drain electrode side overhang distance (e) of 0.15micron which is 5% of the gate drain spacing (g).

Device 2 included a drain electrode side overhang distance (e) of 0.60micron which is 20% of the gate drain spacing (g).

FIG. 14 shows the drain leakage currents of Devices 1 and 2 as afunction of drain-source voltage. In both devices, the drain leakagecurrent was less than 10 mA at all drain-source voltages which isgenerally for FET devices having this gate periphery. The drain leakagecurrent in Device 2 is significantly lower than the drain leakagecurrent in Device 1. For this device design, increasing the overhangdistance (e) from 5% of the gate drain spacing (g) to 20% of the gatedrain spacing resulted in the reduction of the drain leakage current.

Having thus described several aspects of at least one embodiment of thisinvention, it is to be appreciated various alterations, modifications,and improvements will readily occur to those skilled in the art. Suchalterations, modifications, and improvements are intended to be part ofthis disclosure, and are intended to be within the spirit and scope ofthe invention. Accordingly, the foregoing description and drawings areby way of example only.

1. A semiconductor structure comprising: a gallium nitride materialregion; an electrode-defining layer formed over the gallium nitridematerial region and including a via formed therein, a cross-sectionalarea at a top of the via being greater than a cross-sectional area at abottom of the via; and an electrode formed on the gallium nitridematerial region and in the via, wherein the electrode length is definedat the bottom of the via.
 2. The semiconductor structure of claim 1,wherein the electrode is a gate electrode.
 3. The semiconductorstructure of claim 2, further comprising a source electrode formed onthe gallium nitride material region and a drain electrode formed on thegallium nitride material region.
 4. The semiconductor structure of claim3, wherein the gate electrode extends over a portion of the top surfaceof the electrode-defining layer a distance, in a direction of the drainelectrode, of between about 2% and about 60% of a distance between thegate electrode and the drain electrode.
 5. The semiconductor structureof claim 18, wherein the gate electrode extends over a portion of thetop surface of the electrode-defining layer a distance in a direction ofthe drain electrode greater than a distance in a direction of the sourceelectrode.
 6. The semiconductor structure of claim 19, wherein the gateelectrode extends over a portion of the top surface of theelectrode-defining layer a distance, in a direction of the sourceelectrode, of less than 50% the distance the gate electrode extends overthe electrode-defining layer in the direction of the drain electrode. 7.The semiconductor structure of claim 1, wherein the ratio of theelectrode length to a cross-sectional dimension at the top of the via isbetween about 0.50 and 0.95.
 8. The semiconductor structure of claim 1,wherein the ratio of the electrode length to a cross-sectional dimensionat the top of the via is between about 0.75 and 0.90.
 9. Thesemiconductor structure of claim 1, wherein the electrode is a Schottkycontact.
 10. The semiconductor structure of claim 9, further comprisingan ohmic electrode formed on the gallium nitride material region.
 11. ASchottky diode comprising: a gallium nitride material region; anelectrode-defining layer formed over the gallium nitride material regionand including a via formed therein, a cross-sectional area at a top ofthe via being greater than a cross-sectional area at a bottom of thevia, wherein a sidewall of the via extends upward from the bottom of thevia at an angle between about 5 degrees and about 85 degrees anddownward from the top of the via at an angle between about 90 degreesand about 160 degrees; a Schottky electrode formed on the galliumnitride material region and in the via, wherein the electrode length isdefined at the bottom of the via; and an ohmic electrode formed on thegallium nitride material region.
 12. A method of forming a semiconductorstructure comprising: forming an electrode-defining layer on a galliumnitride material region; forming a via in the electrode-defining layersuch that a cross-sectional dimension at a top of the via is greaterthan a cross-sectional dimension at a bottom of the via; forming anelectrode on the gallium nitride material region and in the via, whereina length of the electrode is defined by the bottom of the via.
 13. Themethod of claim 12, comprising forming the via in a plasma etching step.14. The method of claim 13, wherein pressure conditions in the plasmaare between about 1 mTorr and about 100 mTorr.
 15. The method of claim12, wherein the plasma etching step includes maintaining RF powerconditions of less than about 50 Watts.
 16. The method of claim 12,further comprising controlling an angle of a sidewall of the passivatinglayer to extend upward from a bottom surface of the passivating layer tobe between about 5 degrees and about 85 degrees.
 17. A method of forminga transistor comprising: forming an electrode-defining layer on agallium nitride material region; forming a via in the electrode-defininglayer such that a cross-sectional dimension at a top of the via isgreater than a cross-sectional dimension at a bottom of the via and asidewall of the via extends upward from the bottom of the via at anangle between about 5 degrees and about 85 degrees and downward from thetop of the via at an angle between about 90 degrees and about 160degrees; forming a source electrode on the gallium nitride materialregion; forming a drain electrode on the gallium nitride materialregion; and forming a gate electrode on the gallium nitride materialregion and in the via, wherein a length of the gate electrode is definedat the bottom of the via and the ratio of the gate electrode length to across-sectional dimension at the top of the via is between about 0.50and 0.95.
 18. A method of forming a Schottky diode comprising: formingan electrode-defining layer on a gallium nitride material region;forming a via in the electrode-defining layer such that across-sectional dimension at a top of the via is greater than across-sectional dimension at a bottom of the via and a sidewall of thevia extends upward from the bottom of the via at an angle between about5 degrees and about 85 degrees and downward from the top of the via atan angle between about 90 degrees and about 160 degrees; forming anohmic electrode on the gallium nitride material region; and forming aSchottky electrode on the gallium nitride material region and in thevia, wherein the electrode length is defined at the bottom of the via.